清华设计自动化为祖国EDA事业发展而努力！

• 姓名：周强
• 职称：研究员
• 电话：62785564
• 邮箱：zhouqiang@tsinghua.edu.cn

工学学士 (计算机科学与技术), 中国科学技术大学, 中国, 1983;

工学硕士 (计算机科学与技术), 清华大学, 中国, 1986;

工学博士 (控制理论与控制科学), 中国矿业大学（北京）, 中国, 2002.

电子设计自动化, 布图理论与算法

计算机软件与系统

数字系统设计自动化 (课号40240412, 本科);

超大规模集成电路布图理论与算法 (课号70240163, 研究生).

我曾讲授过多门计算机软件方向的本科生和研究生课程，目前正在教授三年级本科生“数字系统设计自动化”课程，研究生“超大规模集成电路布图理论与算法”课程。在教学过程中，我关注于相关领域的最新发展动态，将数字系统设计自动化和集成电路物理设计领域的出现的新问题和新方法引入到课程教学中。在讲解课程相关的图论和组合优化算法的基础上，我将最新的研究成果引介给学生。我注重教学改革，将研究融入到教学中，形成研究型教学模式，同时努力保持课程内容的新颖性和前沿性。在教学过程中，我注重学生的参与，在课堂上鼓励学生参与到问题、算法策略、复杂性的分析过程中，提高学生算法设计能力。

国家重大科技专项课题: 先进EDA工具平台开发 (2008-2010);

国家自然科学基金重点项目: 支持高速缓存一致性的片上网络关键技术研究 (2009-2012);

国家自然科学基金项目: 高可靠低功耗片上时钟设计与优化算法 (2009-2011).

三维IC芯片设计从面积、线长、热的角度，对三维芯片物理设计优化理论与方法进行研究，是延续摩尔定律的新兴研究领域。在三维IC布图规划和布局方向上，我的课题组与Intel公司合作，开展相关算法研究，提出了旨在降低算法复杂度的划分策略、热优化算法、热通孔分配算法；我们开发的工具系统交付Intel公司，受到Intel公司好评，就此发表的论文被2005年IEEE ASICON国际会议评为最佳论文；此外，我们还与美国西北大学合作，首次提出了三维解析式布局算法策略。

在多目标极大规模布局算法的方向，我的课题组结合纳米及超深亚微米工艺IC设计需要，对极大规模、混合模式、旨在解决设计收敛的多目标布局算法进行研究。我们与Intel公司合作提出了大规模混合模式布局优化算法，解决了大模块和标准单元同时安置的难题；我们开发的面向混合模式的布局工具交付Intel公司，被对方评价为“世界一流水平”；我们提出的面向时钟节点规划的布局算法，从设计方法学上解决了时钟设计与布局的融合问题。

在互连线规划与优化方向，低功耗、低热耗和低成品率是目前纳米IC发展的瓶颈。我的课题组早在2004年对该方向进行了深入研究，目前处于国际前沿水平。我们提出了时延、功耗及热的多目标物理优化算法，解决了低功耗的物理设计问题，是国际上较早开展低功耗物理优化算法的团队之一，成果获得ACM GLVLSI 2008国际会议最佳论文奖；我们提出了时钟和电源/地线网络快速分析算法，解决了大规模互连网络分析速度和精度的难题；我们与Intel公司合作，完成封装与P/G协同分析的前瞻性研究课题；此外，我们还与Synopsys公司合作，提出了成品率驱动的布线算法，解决了物理设计阶段与IC制造结合的难题，也是国际上较早开展提高成品率的物理优化算法的团队之一，成果获得ICCAD会议最佳论文提名奖。

在可编程、可重构SOC关键技术方向，我们结合国内在SOC和FPGA设计方面的需要，对其关键技术和优化算法进行研究。在国家自然科学基金重点项目资助下，我们提出了可重构MPGA结构以及针对FPGA的布局、布线算法。我们还受邀主办2010年IEEE FPT国际会议，这是该会议首次在中国大陆召开。

全国第16届计算机辅助设计与图形学学术会议: 程序委员会主席 (2010);

IEEE International Conference on Field-Programmable Technology 2010: 程序委员会主席 (2010).

北京市科学技术二等奖——超深亚微米SOC物理级CAD关键技术及其应用 (2007).

[1] Qiang Zhou, Xin Zhao, Yici Cai, Xainlong Hong, A MTCMOS Technology for Low-Power Physical Design, Integration, the VLSI Journal, vol.42, no. 3, pp. 340–345, 2009.

[2] Junbo Yu, Qiang Zhou, Gang Qu, Bian Jinian, Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol. E92-A, no.12, pp. 3151-3159, 2009.

[3] Haixia Yan, Qiang Zhou, Xianlong Hong, Thermal aware placement in 3D ICs using quadratic uniformity modeling approach, Integration, the VLSI Journal, vol. 42 no.2 pp.175-180, 2009.

[4] Junjun Gu, Gang Qu, and Qiang Zhou, Information Hiding for Trusted System Design, Proceeding of the ACM/IEEE Design Automation Conference（DAC 2009）, San Francisco, CA, pp.698-701.

[5] Wang Xiaoyi, Cai Yici, Zhou Qiang, Sheldon X.-D. Tan, Decoupling Capacitance Budgeting Aware Placement For Transient Power Supply Noise Elimination, Proceedings of ACM/IEEE International Conference on Computer Aided Design(ICCAD 2009), San Jose, CA, pp. 745-751, 2009

[6] Junbo Yu, Qiang Zhou, Jinian Bian. Peak Temperature Control in Thermal-aware Behavioral Synthesis through Allocating the Number of Resources. Proceedings of IEEE Asia South Pacific Design Automation Conference(ASPDAC 2009), Yokohama, Japan, pp. 85-90, 2009.

[7] Cai Yici, Zhou Qiang, Hong Xianlong, Shi Rui, Wang Yang, Applications of Optical Proximity Correction Technology, Science In China, vol. 51, no. 2, pp. 213-224, 2008.

[8] Guo Liangpeng, Cai Yici, Zhou Qiang, Hong Xianlong, Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E91-A, no.8, pp. 2084-2090, 2008.

[9] Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong, A novel performance driven power gating based on distributed sleep transistor network, Proceedings of the 18th ACM Great Lakes symposium on VLSI(GLVLSI 2008), Rhode Island, USA, pp:255-260, 2008.

[10] Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian, Low power clock buffer planning methodology in F-D placement for large scale circuit design, Proceedings of IEEE Asia and South Pacific Design Automation Conference(ASPDAC 2008), Seoul, Korea, pp. 370–375.

[11] Xing Wei, Juanjuan Chen,, Qiang Zhou, Yici Cai,, Jinian Bian,, Xianlong Hong, MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation, International Conference on Field Programmable Logic and Applications( FPL 2008), Heidelberg, Germany, pp.559-562, 2008.

[12] Li Zhuoyuan, Hong Xianlong, Qiang Zhou, Shan Zeng, Bian Jinian, Wenjian Yu, Yang H.H., Pitchumani V., Chung-Kuan Cheng, Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 4, pp.645–658, 2007.

[13] Zhou Qiang, Cai Yici, Li Duo, Hong Xianlong, A yield-driven gridless router, Journal of Computer Science and Technology, vol. 22, no. 5, pp.653-660, 2007.

[14] Cai Yici, Liu Bin, Zhou Qiang, Hong Xianlong, Voltage island generation in cell based dual-Vdd design, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no 1, pp. 267-273, 2007.

[15] Lu Yongqiang, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu, An Efficient Quadratic Placement Based On Search Space Traversing Technology, Integration, VLSI journal, vol.40, no. 3, pp. 253-260, 2007.

[16] 蔡懿慈, 周强, 洪先龙, 石蕊, 王旸, 光学邻近效应矫正(OPC)技术及其应用, 中国科学 E 辑: 信息科学, 第37卷, 第12期, 1607-1619, 2007.

[17] Zhou Pingqiang, Yuchun Ma, Zhuoyuan Li, Robert Dick, Li Shang, Xianlong Hong, Qiang Zhou, 3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-Dimensional Integrated Circuits, Proceedings of ACM/IEEE International Conference on Computer Aided Design(ICCAD 2007), San Jose, CA, pp. 590-597, 2007.

[18] Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Yang, Vijay Pitchumani. Efficient Thermal-oriented 3D Floorplanning Algorithm And Thermal Via Planning For Two-stacked-die Integration. ACM Transactions on Design Automation of Electronic Systems, vol.11 no.2, pp.325-345, 2006.

[19] Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Yang, Vijay Pitchumani, Chung-Kuan Cheng. Hierarchical 3-D Floorplanning Algorithm For Wirelength Optimization. IEEE Transactions on Circuits And Systems - I : Fundamental Theory and Applications,vol. 53, no. 12, pp。2637-2646, 2006.

[20] Cai Yici, Liu Bin, Zhou Qiang, Hong Xianlong, A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment, IEEE Transactions on CAS-II, vol.53, no. 10, pp1007-1011, 2006.

[21] Yao Hailong, Cai Yici, Zhou Qiang, Hong Xianlong, Multilevel Routing with Redundant Via Insertion, IEEE Transactions On CAS-II, vol.53, no. 10, pp.1148-1152, 2006.

[22] Cai Yici, Liu Bin, Zhou Qiang, Hong Xianlong, Priority-Based Routing Resource Assignment Considering Crosstalk, Journal of Computer Science and Technology, vol.21, no.6, pp. 913-921, 2006.

[23] Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Yang, Vijay Pitchumani, Chung-Kuan Cheng. Integrating Dynamic Thermal Via Planning With 3D Floorplanning Algorithm. ACM/SIGDA International Symposium on Physical Design( ISPD 2006), San Jose, pp.178-185, 2006.

[24] Liu Bin, Cai Yici, Zhou Qiang, Hong Xianlong, Power Driven Placement with Layout Aware Supply Voltage Assignment for Voltage Island Generation in Dual-Vdd Designs, The Proceeding of 11th IEEE/ACM Asia & South Pacific Design Automation Conference (ASP-DAC2006), Yokohama, Japan, pp. 582-587, 2006.

[25] Zhuoyuan Li, Hiaxia Yan, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Yang, Vijay Pitchumani. Design Tools For 3D Mixed Mode Placement. IEEE International Conference on ASIC(ASICON 2005), Shanghai, vol.2 pp.792-796, 2005.