Jianlei Yang

PhD Student
Electronic Design Automation Laboratory
Department of Computer Science and Technology
Tsinghua University

I received the B.S. degree in Microelectronics, Xidian University in 2009, and the Ph.D degree in the Department of Computer Science and Technology, Tsinghua University in 2014, supervised by Prof. Yici Cai.

My research interests include: Microelectronics and Integrated Circuits, VLSI physical design, Power grid analysis and optimization, Numerical Algorithms.

For more information, please refer to my C.V. here. (last updated Sept. 13th, 2014)

Contact Me
Email: jerryyangs AT gmail DOT com
Address: Room 8-404, East Main Building, Tsinghua University, Beijing, P. R. China, 100084

[Education] [Publications] [Teaching] [Projects] [Patents] [Prizes and Honors] [Services] [Academic Activities] [Invited Talks] [Software] [Personal] [Links]

News:

  • 08/29/2013, ICCD Best Paper Award! (Tsinghua CS News)
  • 10/10/2012, The IBM Chinese Excellent Student Scholarship! (CSC News)
  • 01/20/2012, Second Place Winner of TAU Transient Power Grid Simulation Contest! (TAU)
  • 04/09/2011, First Place Winner of TAU Power Grid Simulation Contest! (TAU Contest)

Education and Experience:

  • 9/2009-7/2014: Ph.D Degree, Department of Computer Science and Technology, Tsinghua University.
  • 9/2005-7/2009: Bachelor Degree, Department of Microelectronics, Xidian University.

  • 7/2013-7/2014: Research Intern in Intel Labs China, Beijing.
  • July, 2012, Intern in Nimbus Automation Technologies, Shanghai.

Publications: [DBLP] [Google Scholar Citations]

  Journal Publications:
  1. Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao. A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification, accepted by IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI).
  2. Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou. PowerRush: An Efficient Simulator for Static Power Grid Analysis, to appear on IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI).
  3. Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi. Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2014, 22(4):899-912.
  Conference/Workshop Publications:
  1. Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai. Early Stage Real-Time SoC Power Estimation Using RTL Instrumentation, 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015): 779-784, 2015.
  2. Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou. Power Supply Noise Aware Evaluation Framework for Side Channel Attacks and Countermeasures, International Conference on Field-Programmable Technology (FPT 2014): 161-166, 2014, (Invited Paper by Special Session of Hardware Security).
  3. Wei Zhao, Yici Cai, Jianlei Yang. Fast Vectorless Power Grid Verification using Maximum Voltage Drop Location Estimation, 19th Asia and South Pacific Design Automation Conference (ASP-DAC 2014): 861-866, Singapore, 2014.
  4. Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao. Selected Inversion for Vectorless Power Grid Verification by Exploiting Locality, IEEE International Conference on Computer Design (ICCD2013): 257-263, Asheville, 2013. (Best Paer Award)
  5. Wei Zhao, Yici Cai, Jianlei Yang. A Multilevel H-matrix-based Approximate Matrix Inversion Algorithm for Vectorless Power Grid Verification, 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013): 163-168, Yokohama, 2013.
  6. Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou. PowerRush: Efficient Transient Simulation for Power Grid Analysis, IEEE/ACM International Conference on Computer-Aided Design (ICCAD2012): 653-659, San Jose, 2012, (Invited Paper by Special Session of Power grid simulation and verification for billion-transistor VLSI designs).
  7. Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou. PowerRush: A Linear Simulator for Power Grid, IEEE/ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU2012), Taipei, 2012. (Invited Paper).
  8. Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi. Fast Poisson Solver Preconditioned Method for Robust Power Grid Analysis, IEEE/ACM International Conference on Computer-Aided Design (ICCAD2011): 531-536, San Jose, 2011.
  9. Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou. PowerRush: A Linear Simulator for Power Grid, IEEE/ACM International Conference on Computer-Aided Design (ICCAD2011): 482-487, San Jose, 2011, (Invited Paper by Special Session of 2011 TAU Power Grid Contest).
  10. Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin-Ngai Sze. Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization, ACM Great Lakes Symposium on VLSI 2011: 199-204, Lausanne, 2011.

Teaching:

  • Teaching Assistant, Spring, 2014, Numerical Analysis, Tsinghua University, Undergraduate Course, Prof. Yici Cai.
  • Teaching Assistant, Fall, 2013, Introduction to VLSI Design, Tsinghua University, Undergraduate Course, Prof. Yici Cai.
  • Teaching Assistant, Fall, 2013, Introduction of VLSI Design, Tsinghua University, Graduate Course, Prof. Yici Cai.
  • Teaching Assistant, Spring, 2013, Design Automation for Digital Systems, Tsinghua University, Undergraduate Course, Prof. Qiang Zhou.
  • Teaching Assistant, Spring, 2013, The Layout Theories and Algorithms for VLSI, Tsinghua University, Graduate Course, Prof. Qiang Zhou.
  • Teaching Assistant, Fall, 2012, Introduction to VLSI Design, Tsinghua University, Undergraduate Course, Prof. Yici Cai.
  • Teaching Assistant, Fall, 2012, Introduction of VLSI Design, Tsinghua University, Graduate Course, Prof. Yici Cai.
  • Teaching Assistant, Summer, 2012, Program Design and Training, Tsinghua University, Undergraduate Course, Prof. Hailong Yao.
  • Teaching Assistant, Spring, 2012, Numerical Analysis, Tsinghua University, Undergraduate Course, Prof. Yici Cai.
  • Teaching Assistant, Fall, 2011, Introduction to VLSI Design, Tsinghua University, Undergraduate Course, Prof. Yici Cai.
  • Teaching Assistant, Fall, 2011, Introduction of VLSI Design, Tsinghua University, Graduate Course, Prof. Yici Cai.
  • Teaching Assistant, Spring, 2011, The Layout Theories and Algorithms for VLSI, Tsinghua University, Graduate Course, Prof. Qiang Zhou.
  • Teaching Assistant, Fall, 2010, Introduction to VLSI Design, Tsinghua University, Undergraduate Course, Prof. Yici Cai.
  • Teaching Assistant, Fall, 2010, Introduction of VLSI Design, Tsinghua University, Graduate Course, Prof. Yici Cai.
  • Teaching Assistant, Spring, 2010, Numerical Analysis, Tsinghua University, Undergraduate Course, Prof. Yici Cai.
  • Teaching Assistant, Fall, 2009, Introduction to VLSI Design, Tsinghua University, Undergraduate Course, Prof. Yici Cai.
  • Teaching Assistant, Fall, 2009, Introduction of VLSI Design, Tsinghua University, Graduate Course, Prof. Yici Cai.

Projects:

  • SelInv: Selected Inversion for Vectorless Power Grid Verification. Jianlei Yang, Wei Zhao, Prof. Yici Cai, Prof. Qiang Zhou.
  • PowerRushTran: Efficient Transient Power Grid Simulation. Jianlei Yang, Zuowei Li, Prof. Yici Cai, Prof. Qiang Zhou.
  • PowerRush: A Linear Simulator for Static Power Grid Analysis. Jianlei Yang, Zuowei Li, Prof. Yici Cai, Prof. Qiang Zhou and Prof. Yuchun Ma.
  • SPEX: Specific Parasitic Devices Extraction for Analog Integrated Circuits. Jianlei Yang, Prof. Yici Cai and Prof. Qiang Zhou, Based on OpenAccess platform we developed an commercial tool for specific parasitic devices extraction for high voltage / high power process.

Patents:

  1. Yici Cai, Qiang Zhou, Jianlei Yang, A Transient Simulation Method for On-Chip Power Grid with RCL Network, Apply Number: 201310152859.X, Apply Date: 2013-04-27, Public Number: 103207941A, Public Date: 2013-07-17. [SooPAT]
  2. Yici Cai, Qiang Zhou, Jianlei Yang, Zuowei Li, A Simulation Method for On-Chip Power Grid, Apply Number: 201210073172.2, Apply Date: 2012-03-19, Public Number: 102663166A, Public Date: 2012-09-12. [SooPAT]
  3. Qiang Zhou, Yici Cai, Zuowei Li, Jianlei Yang, A Construction Method of Conductance Matrix for On-Chip Power Grid Simulation, Apply Number: 201210058929.0, Apply Date: 2012-03-07, Public Number: 102646143A, Public Date: 2012-08-22. [SooPAT]
  4. Qiang Zhou, Yici Cai, Zuowei Li, Jianlei Yang, An Adaptive Method of Handling Metal Vias for On-Chip Power Grid Simulation, Apply Number: 201210058540.6, Apply Date: 2012-03-07, Public Number: 102592033A, Public Date: 2012-07-18, Grant Date: 2013-07-24. [SooPAT]
  5. Yici Cai, Qiang Zhou, Jianlei Yang, A Friendly Extraction Method of Specific Parasitic Devices for Analog Integrated Circuits, Apply Number: 201010262309.X, Apply Date: 2010-08-25, Public Number: 1923595A, Public Date: 2010-12-22, Grant Date: 2012-10-24. [SooPAT]

Prizes and Honors:

Services:

Academic Activities:

  • Review for: DAC, ICCAD, TCAD, TODAES, ASPDAC, Integration the VLSI, VLSI-DAT.

Invited Talks:

  • I'm invited by IWECS 2011 (held in Hangzhou) to give a talk in "Fast Poisson Solver Preconditioned Method for Power Grid Analysis".

Personal:

  • Quotes: People say we should seek fun, not risk. I say I seek risk as fun. People say we can't foresee the future. I say if we can't, create it.
  • Electronic Design Automation by this interesting video: Where Electronics Begins from EDAC.
  • One of my favorite articles likes this: The best of ICCAD
  • The most exciting activity in EDA area is DAC.

Links: