Hi, my name is Yu Bei, a M.S. student in Department of Computer Science, Tsinghua University, Beijing, China. I got my B.S. in School of Applied Mathematics, UESTC.    I work in the EDA Lab, and my advisor is Sheqin Dong. My research interests include CAD for VLSI, floorplanning algorithms and low power design.

[Education]  [Public]  [Research] [Honors] [CV] [Courses] [Links]  [Contact Me]

Education Background

• M.S.(2007.9--2010.7)     Department of Computer & Technology,   Tsinghua University, China.  

            Overall GPA:  89.7/100  (Top 10% of 160+)

• B.S.(2003.9--2007.7)    Info & Compute Science,   Univ. Elec Science & Tech of China                            

            Overall GPA: 3.59/4.0,       Major GPA: 3.65/4.0(Top 10% of 120+)

• Visited Student (2008.9-2008.12,  2009.5-2009.8)      IPS, Waseda University,  Japan.

Journal Paper

• Bei Yu, Sheqin Dong, Song Chen, and Satoshi GOTO, "Voltage and Level-Shifter Assignment Driven Floorplanning", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E92-A, NO.12, Dec. 2009.

Conference Papers

• Bei Yu, Sheqin Dong, Song Chen, and Satoshi GOTO, "Floorplanning and Topology Generation for Application-Specific Network-on-Chip", in IEEE Proc. Asia and South Pacific Design Automation Conference
  (ASPDAC), 2010.

• Bei Yu, Sheqin Dong, Song Chen, and Satoshi GOTO, "Voltage-Island Driven Floorplanning Considering Level-Shifter Positions", in ACM Proc. Great Lakes Symposium on VLSI (GLSVLSI), 2009.

• Bei Yu, Sheqin Dong and Satoshi GOTO, "Multi-Voltage and Level-Shifter Assignment Driven Floorplanning", in IEEE Proc. ASICON 2009.

• Tao Lin, Sheqin Dong, Bei Yu, Song Chen and Satoshi GOTO, "A Revisit to Voltage Partitioning Problem", in ACM Proc. Great Lakes Symposium on VLSI (GLSVLSI), 2010.

Research Interests

        Low Power Circuit, Physical Design, Logic Synthesis, Network-on-Chips Design. (For more details, click here.)

Academic Experience

• 2007/7--present    Tsinghua University, Beijing, China               Research Assistant
  
  • Floorplanning tool with symmetry constraints, using B*-tree and Sequence Pairs.
  • Two phases placement tool VLSAF to solve voltage and level shifter assignment problem. (relative work was accepted by ACM Proc. GLSVLSI 2009)
  • Implemented and evaluated a couple of other approaches to voltage assignment problem.
  • Extended VLSAF to a new placement tool MVLSAF by supporting arbitrary number of legal voltages in voltage assignment problems. (relative work was accepted by IEEE Proc. ASICON 2009)
  • Co-work with other students, revisited voltage partitioning problem, proposed an optimal algorithm running in polynomial time. (relative work was accepted by ACM Proc. GLSVLSI 2010)

• 2008/5--2009/8    Waseda University, Kitakyushu, Japan         Visiting Student
  • Co-work with other students on Through-Silicon Via Planning for 3-D SoCs (relative work was submitted to IEEE Proc. ISCAS 2010).
  • Co-work with other students on developing new communication protocols, which can have significant impact on the overall energy dissipation in Wireless Sensor Networks.
  • Proposed, implemented and evaluated a topology generation and floorplanning tool for application-specific Network-on-Chips (NoCs). (relative work was accepted by IEEE Proc. ASPDAC 2010)

• 2009/1--2009/5     JEDA Technologies, Beijing, China                   Internship
  • Implemented and tested on JEDAcc, which is a code coverage tool for programs written in C or C++ languages.
  • Tested on JEDA IDE, which is a pack of integrated GUI tools for JEDAcc.

Honors

• 2009                Guanghua First Class Scholarship,                    Tsinghua Univ.
• 2009                Cadence Second Class Scholarship,                   Cadence
• 2006                Second Prize Excellence Scholarship,               Univ. Elec Science & Tech of China
• 2006                Third Prize in ACM Programming Context,    Univ. Elec Science & Tech of China
• 2005                Second Prize Excellence Scholarship,               Univ. Elec Science & Tech of China
• 2004                Second Prize Excellence Scholarship,               Univ. Elec Science & Tech of China

Core Courses

Resume

• Yu-Bei-Resume.pdf

Useful Links

• Tips for Short Talk
• DAC
• ICCAD
• ASPDAC
• DATE
• ISQED
• GLSVLSI

Contact Me

       disyulei AT gmail DOT com     

       b-yu07 AT mails DOT tsinghua DOT edu DOT cn

Created: 10/26/2009,